Nanowires are attracting increasing interest due to their physical properties and use in various nano devices. In semiconductor devices nanowires are used as building blocks for the fabrication of photonics and electronic nano devices and in sensors in particular. Semiconductor devices also use nanowires for various purposes. These include to form connections, such as a transistor channel, between various electrodes of transistors found in microcircuits manufactured by a CMOS process. The nanowires can be of silicon which has the advantage of a fairly easy integration into existing silicon device technology together with the reproducible control of their electronic properties.
A top-down fabrication procedure is often used in the fabrication of devices that use silicon nanowires. The top-down fabrication procedure is similar to that used in the fabrication of CMOS devices. In this procedure there is a substrate, usually of silicon, having a buried silicon oxide (BOX) layer on its top surface on which a silicon nanowire is located. The silicon nanowire can be formed by chemical vapor deposition of Si onto the BOX layer or on SOI wafers or by other well-known techniques.
In one type of such a transistor device a nanowire spans a well, much like a beam. The well is an etched out area of the BOX layer into which a gate electrode of the transistor is to be formed. Various processing steps are carried out from the top of this type of nanowire product. One such step is the thinning of a part of the nanowire beam that spans the well for the purpose of forming an ultra-thin transistor channel. In this step the wire portion is thinned by oxidation. To accomplish the oxidation thinning of a selected part of the nanowire a hard mask is deposited over portions of the wire and BOX layer that are not to be etched away by oxidation. A hard mask is a suitable material that is not affected by oxidation, one such material being silicon nitride. The hard mask has an open portion, called a window, through which oxidation of the selected part of the nanowire can take place.
Problems are sometimes encountered with the process of selective oxidation that takes place through the hard mask window. The problems sometimes cause the silicon nanowire structure to break at the region where the nanowire beam under the mask is in contact with the BOX layer, that is, where an end of the nanowire beam is supported on its BOX layer. The diffusion of oxygen through the BOX layer during the oxidation process enhances the local oxidation at the ends of the beam supported on the BOX layer. This causes a thinning of the silicon nanowire in these regions thereby producing areas where the beam support is weakened. When the nanowire is scaled to smaller dimensions, such as below 20 nm, these regions may result in a break in the nanowire structure due to stress.
Accordingly, a need exists to improve the fabrication process in a manner so that the product, such as a transistor, that is produced with the nanowire does not have the nanowire breakage problem.